EE61204: Power Management Integrated Circuits

Venue: NR-223 (Nalanda Class Complex)
Class Timings: Monday (15:00-16:55), Tuesday (14:00-15:55)
References:
[1] Power Management Techniques for Integrated Circuit Design By Ke-Horng Chen, Wiley-Blackwell, 2016
[2] Power Management Integrated Circuits by M.M. Hella and P.P. Mercier (eds.), CRC Press, 2016
[3] Fundamentals of Power Electronics, 2nd Edition by Robert W. Erickson, Dragan Maksimovic, Springer (India) Pvt. Ltd, 2005
[4] Reconfigurable Switched-Capacitor Power Converters by D. Ma, R. Bondade, Springer
[5] Design of Analog CMOS Integrated Circuits by Bezad Razavi, Tata McGraw-Hill
    Class-1,2: Course introduction
    Class-3: Introduction to Power Management Integrated Circuits
    Class-4: Few State-of-Art Designs
    Voltage and Current References:
    Class-5: Supply-independent current biasing
    Class-6: Voltage to current converter
    Class-7: Voltage reference, NTC Voltage, PTC Voltage
    Class-8: Bandgap Reference
    Class-9: PTAT current reference, Sub 1-V Bandgap Reference
    Class-10: Numerical Problems
    Impact of Technology in Power Management IC:
    Class-11: Power MOSFETs and Isolation Technology, DMOS, LDMOS, HVMOS
    Class-12: Power MOSFETs and Isolation Technology, DMOS, LDMOS, HVMOS
    Linear Regulators:
    Class-13: Conceptual development of linear regulator, classifications
    Class-14: Numerical Problems
    Class-15: Analytical model, different specifications
    Class-16: Numerical Problems
    Class-17: Single-stage topology and different variants
    Class-18: Single-stage topology: DC analysis
    Class-19: Single-stage topology: small signal analysis and pole movements
    Class-20: Single-stage topology: small signal analysis and pole movements, slewing response
    Class-21: Two-stage topology and DC analysis for different variants
    Class-22: Two-stage topology: small signal analysis and pole movements, slewing response
    Class-23: Three-stage topology: with-capacitor case and pole movements.
    Class-24: Three-stage topology: capacitor-less case, nested Miller compensation and pole movements.
    Class-25: Digital LDO
    Class-26: System-level considerations of linear regulator