RESEARCH PUBLICATIONS

Publications in Journals

1.              K. Manna, P. Mukherjee, S. Chattopadhyay and I. Sengupta, “Thermal-aware test scheduling strategy for network-on-chip based systems”, ACM Journal of Emerging Technologies in Computing Systems (JETC) (Accepted).

2.              A. Chatterjee and I. Sengupta, “Sorting of fully homomorphic encrypted cloud data: can partitioning be effective?”, IEEE Transactions on Services Computing (Accepted).

3.              V. Agarwal, A. Singla, M. Samiuddin, S. Roy, T-Y. Ho, I. Sengupta and B.B. Bhattacharya, “Scheduling algorithms for reservoir- and mixer-aware sample preparation with microfluidic biochips”, Integration: The VLSI Journal, DOI: https://doi.org/10.1016/j.vlsi.2018.01.002, 2018.

4.              R. Gharpinde, P.L. Thangkhiew, K. Datta and I. Sengupta, “A scalable in-memory logic synthesis approach using memristor crossbar”, IEEE Transactions on VLSI Systems, Vol. 26, No. 2, pp. 355-388, February 2018.

5.              A. Kole, K. Datta and I. Sengupta, “A new heuristic for N-dimensional nearest neighbor realization of a quantum circuit”, IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 37, No. 1, pp. 182-192, January 2018.

6.              K. Manna, P. Mukherjee, S. Chattopadhyay and I. Sengupta, “Thermal-aware application mapping strategy for network-on-chip based system design”, IEEE Transactions on Computers, Vol. 67, No. 4, pp. 528-542, April 2018.

7.              A. Chatterjee and I. Sengupta, “Translating algorithms to handle fully homomorphic encrypted data on the cloud”, IEEE Transactions on Cloud Computing, Vol. 6, No. 1, pp. 287-300, January 2018.

8.              S. Dhal and I. Sengupta, “A new object searching protocol for multi-tag RFID”, Wireless Personal Communications, Vol. 97, No. 3, pp. 3547-3568, December 2017.

9.              B. Ghoshal, C. Mandal and I. Sengupta, “Refresh re-use based transparent test for detection of in-field permanent faults in DRAMs”, Integration: The VLSI Journal, Vol. 59, Issue C, pp. 168-178, September 2017.

10.          A. Kole, K. Datta and I. Sengupta, “A heuristic for linear nearest neighbor realization of quantum circuits by SWAP gate insertion using N-gate lookahead”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 6, No. 1, pp. 62-72, January 2016.

11.          A. Bhar, S. Chattopadhyay, I. Sengupta and R. Kapur, “Small test set generation with high diagnosability”, Journal of Circuits, Systems and Computers, Vol. 25. No. 4, April 2016.

12.          B. Ghoshal, K. Manna, S. Chattopadhyay and I. Sengupta, “In-field test for permanent faults in FIFO buffers of NoC routers”, IEEE Transactions on VLSI Systems, Vol. 24, No. 1, pp. 393-397, January 2016.

13.          K. Manna, S. Swamy, S. Chattopadhyay and I. Sengupta, “Integrated through silicon via placement and application mapping for 3D mesh based NoC design”, ACM Transactions on Embedded Computing Systems (TECS), Vol. 16, Issue 1, Article No. 24, November 2016.

14.          K. Datta, T. Chattopadhyay and I.Sengupta, “All optical design of binary adders using semiconductor optical amplifier assisted Mach-Zehnder interferometer”, Microelectronics Journal, Elsevier, Vol. 46, No. 9, pp. 839-847, September 2015.

15.          S. Kundu, S. Chattopadhyay, I. Sengupta and R. Kapur, “Scan-chain masking for diagnosis of multiple chain failures in a space compaction environment”, IEEE Transactions on VLSI Systems (TVLSI), Vol. 23, No. 7, pp. 1185-1195, July 2015.

16.          K. Datta, G. Rathi, I. Sen Gupta and H. Rahaman, “Exact synthesis of reversible circuits using Astar algorithm”, Journal of the Institution of Engineers: Series B, Springer, Vol. 96, No. 2, pp. 121-130, July 2015.

17.          B. Mazumdar, D. Mukhopadhyay and I. Sengupta, “Construction of RSBFs with improved cryptographic properties to resist differential fault attack on Grain family of stream ciphers”, Cryptography and Communications, Vol. 7, No. 1, pp. 35-69, January 2015.

18.          K. Manna, C. Reddy, S. Chattopadhyay and I. Sengupta, “Thermal-aware multi-frequency network-on-chip testing using particle swarm optimization”, Journal of High Performance Systems Architecture, Inderscience, Vol. 5, No. 3, pp. 141-152, 2015.

19.          K. Datta, I. Sen Gupta and H. Rahaman, “A post-synthesis optimization technique for reversible circuits exploiting negative control lines”, IEEE Transactions on Computers, Vol. 64, No. 4, pp. 1208-1214, April 2015.

20.          K. Datta, I. Sengupta, H. Rahaman and R. Drechsler, “An approach to reversible logic synthesis using input and output permutations”, Springer Transactions on Computational Science, Vol. 8911, pp. 92-110, December 2014.

21.          K. Datta, G. Rathi, I. Sen Gupta and H. Rahaman, “An improved reversible circuits synthesis approach using clustering of ESOP cubes”, ACM Journal of Emerging Technologies in Computing Systems (JETC), Vol. 11, No. 2, Article 15, November 2014.

22.          P. Chatterjee, U. Ghosh, I. Sengupta and S. K. Ghosh, “Approach for modeling trust in cluster-based wireless ad hoc networks”, IET Networks, Vol. 3, No. 3, pp. 187-192, 2014.

23.          P. Chatterjee, U. Ghosh, I. Sengupta and S. K. Ghosh, “A trust enhanced secure clustering framework for wireless ad hoc networks”, Wireless Networks, Vol. 20, No. 7, pp. 1669-1684, 2014.

24.          K. Datta, I. Sen Gupta and H. Rahaman, “PSO based reversible circuit synthesis using mixed control Toffoli gates”, Journal of Low Power Electronics (JOLPE), American Scientific Publishers, Vol. 9, No. 3, pp. 363-372, October 2013.

25.          B. Mazumdar, D. Mukhopadhyay amd I. Sen Gupta, “Constrained search for a class of good bijective S-boxes with improved DPA resistivity”, IEEE Transactions on Information Forensics & Security, Vol. 8, No. 12, pp. 2154-2163, December 2013.

26.          S. Kundu, S. Pal, S. Chattopadhyay, I. Sen Gupta and R. Kapur, “A metric for test set characterization and customization towards fault diagnosis”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 32, No. 11, pp. 1824-1828, November 2013.

27.          S. Kundu, A. Jha, S. Chattopadhyay, I. Sen Gupta and R. Kapur, “A framework for multiple fault diagnosis based on multiple fault simulation using particle swarm optimization”, IEEE Transactions on VLSI Systems (TVLSI), Vol. 22, No. 3, pp. 696-700, March 2014.

28.          A. Basu, I. Sen Gupta, and J.K. Sing, “Cryptosystem for secret sharing with hierarchical groups”, International Journal of Network Security, Vol. 15, No. 6, pp. 375-384, June 2013.

29.          K. Datta and I. Sen Gupta, “Partial encryption and watermarking scheme for audio files with controlled degradation of quality”, Multimedia Tools and Applications, Vol. 64, No. 3, pp. 649-669, March 2013.

30.          P. Chatterjee, I. Sen Gupta and S.K. Ghosh, “STACRP: a secure trusted auction oriented clustering based routing protocol for MANET”, Journal of Cluster Computing, Vol. 15, No. 3, pp. 303-320, September 2012.

31.          A. Chatterjee and I. Sen Gupta, “Design of a high performance Binary Edwards Curve based processor secured against side channel analysis”, Integration, the VLSI Journal, Vol. 45, No. 3, pp. 331-340, March 2012.

32.          A. Basu, I. Sen Gupta and J.K. Sing, “Secured hierarchical secret sharing using ECC based signcryption”, Security and Communication Networks, Vol. 5, No. 7, pp. 752-763, July 2012.

33.          V. Bhat, I. Sen Gupta and A. Das, “A new audio watermarking scheme based on singular value decomposition and quantization”, Journal of Circuits, Systems, and Signal Processing, Springer, Vol. 30, No. 5, pp. 915-927, October 2011.

34.          A. Basu, I. Sen Gupta and J.K. Sing, “Proactive verifiable secret sharing scheme using ECC based signcryption”, Journal of Information Assurance and Security, Vol. 5, No. 3, pp. 209-217, 2010.

35.          A.K. Das and I. Sen Gupta, “A location-based key establishment scheme for static wireless sensor networks with multiple base stations”, Journal of Information Assurance and Security, Vol. 5, No. 4, pp. 426-436, 2010.

36.          T. De, A. Pal and I. Sen Gupta, “Traffic grooming, routing and wavelength assignment in optical WDM mesh network based on clique partitioning”, Photonic Network Communications, Vol. 20, No. 2, pp. 101-112, October 2010.

37.          V. Bhat, I. Sen Gupta and A. Das, “An adaptive audio watermarking scheme based on singular value decomposition in wavelet domain”, Digital Signal Processing, Elsevier, Vol. 20, No. 6, 2010.

38.          V. Bhat, I. Sen Gupta and A. Das, “An audio watermarking scheme using singular value decomposition and dither modulation quantization”, Multimedia Tools and Applications, Vol. 52, No. 2-3, pp. 369-383, April 2011.

39.          R.K. Paul and I. Sen Gupta, “Enhancing file data security in Linux operating system by integrating secure file system”, Journal of Information Assurance and Security, Vol. 4, pp. 484-492, 2009.

40.          M. Alam, S. Ghosh, M.J. Mohan, D. Mukhopadhyay, D. Roy Chowdhury and I. Sen Gupta, “Effect of glitches against masked AES S-box implementation and countermeasure”, IET Information Security Journal, pp. 1-11, 2009.

41.          S. Ghosh, M. Alam, D. Roy Chowdhury and I. Sen Gupta, “Parallel crypto-devices for GF(p) elliptic curve multiplication resistant against side channel attacks”, Computers and Electrical Engineering, Vol. 35, pp. 329-338, 2009. 

42.          R. Datta, S. Ghose and I. Sen Gupta, “Two new algorithms for static virtual topology design in WDM optical networks”, Intl. Journal on Wireless and Optical Communications, Vol. 4, No. 1, April 2007. 

43.          R. Datta and I. Sen Gupta, “Static and dynamic connection establishment in WDM optical networks: a review”, IETE Journal of Research, Vol. 51, No. 3, March 2005.

44.          P. Kulkarni and I. Sen Gupta, “Dual and multiple token based approaches for load balancing”, Journal of Systems Architecture, Vol. 51, No. 2, pp. 95-110, February 2005.

45.          R. Datta, B. Mitra, S. Ghose and I. Sen Gupta, “An algorithm for optimal assignment of a wavelength in a tree topology and its applications in WDM networks”, IEEE Journal on Selected Areas in Communication, Vol. 22, No. 9, pp.1589-1600, November 2004.

46.          R. Datta, A.K. Turuk, S. Ghose, R. Kumar and I. Sen Gupta, “New schemes for connection establishment in GMPLS environment for WDM networks”, International Journal on Wireless and Optical Communications, Vol. 2, No. 1, January 2004.

47.          P. Dasgupta, S. Chattopadhyay and I. Sen Gupta, “Cellular automata based recursive pseudo-exhaustive test pattern generation”, IEEE Transactions on Computers, Vol. 50, No. 2, pp.177-185, February 2001.

48.          S. Basu, I. Sen Gupta, D. Roy Chowdhury and S. Bhawmik, “An integrated approach to testing embedded cores and interconnects using test access mechanism (TAM) switch”, Journal of Electronic Testing: Theory and Applications, Vol. 18, No. 4, pp. 475-485, August 2002.

49.          P. Dasgupta, S. Chattopadhyay and I. Sen Gupta, “Theory and application of non-group cellular automata for message authentication”, Journal of Systems Architecture, Vol. 47, No. 7, pp. 383-404, July 2001.

50.          H.K. Pati, R. Mall and I. Sen Gupta, “An efficient bandwidth reservation and call admission control scheme for mobile networks”, Journal of Computer Communications, Vol. 25, No. 1, pp. 74-83, January 2002.

51.          G. Bandyopadhyay, I. Sen Gupta and T.N. Saha, “Use of client-server model in power system loadflow computation”, Intl. Journal of Electrical Power and Energy Systems, pp. 45-49, February 1998.

52.          G.P. Biswas, P. Krishna, I. Sen Gupta and P. Dutta, “Cellular architecture for affine transforms on raster images”, Proceedings IEE - Part E, pp. 103-110, Vol. 143, No. 10, March 1996.

53.          S.S. Nath and I. Sen Gupta, “A Byzantine fault tolerant scheme for error correcting circuits”,  Intl. Journal of System Sciences, pp. 211-217, May 1998.

54.          G.P. Biswas and I. Sen Gupta, “Testable design of combinational networks with a new compaction scheme”, Intl. Journal of Systems Science, pp. 102-113, February 1997.

55.          G. Bandyopadhyay, I. Sen Gupta and T.N. Saha, “Use of client-server model in power system loadflow computation'',  Intl. Journal of Electrical Power and Energy Systems, pp. 45-49, February 1998.

56.          D. Roy Chowdhury, I. Sen Gupta and P. Pal Chaudhuri, “A low-cost high-capacity associative memory design using cellular automata”, IEEE Transactions on Computers, Vol. 44, No. 10, pp.1260-1264, October 1995.

57.          D. Roy Chowdhury, I. Sen Gupta and P. Pal Chaudhuri, “CA based byte error correcting code”, IEEE Transactions on Computers, Vol. 44, No. 3, pp. 371-382, March 1995.

58.          D. Roy Chowdhury, I. Sen Gupta, S. Basu and P. Pal Chaudhuri, “Cellular automata based error correcting codes (CAECC)”, IEEE Transactions on Computers, Vol. 43, No. 6, pp. 759-764, June 1994.

59.          D. Roy Chowdhury, I. Sen Gupta and P. Pal Chaudhury, “A class of two-dimensional cellular automata and applications in random pattern testing”,  Journal of Electronic Testing and Applications, U.S.A., Vol. 5, pp. 65-80, June 1994.

60.          D. Roy Chowdhury, I. Sen Gupta and P. Pal Chaudhuri, “Cellular automata based pattern generator for testing RAM”,  IEE Proceedings - Part E, U.K.,  Vol. 139, No. 6, pp. 469-476, November 1992.

61.          U.K. Bhattacharyya, G. Mohan and I. Sen Gupta, “Parallel fault simulator on a multiprocessor”, Intl. Journal of System Sciences, U.K., Vol. 23, No. 1, pp. 2025-2035, November 1992.

62.          D. Roy Chowdhury and I. Sen Gupta, “Modelling and simulation of  combinational  digital circuits using Petri nets”, Intl. Journal of System Sciences, U.K., Vol. 21, No. 8, pp. 1508-1513, August 1990.

63.          I. Sen Gupta, “Detection of all single and multiple stuck-at faults in combinational circuits using index vector testing”, Intl. Journal of System Sciences, U.K., Vol. 21, No. 8, pp. 1489-1502, August 1990.

64.          S.K. Das, P. Mukherjee and I. Sen Gupta, “Vertex-edge adjacency matrix of a graph and an algorithm to generate all cliques”, Congressus Numerantium, Canada, Vol. 70, pp. 29-40, January 1990.

65.          I. Sen Gupta, “On the minimization of interfaces and interconnections in a digital system satisfying concurrency constraints”, Intl. Journal of System Sciences, U.K., Vol. 20, No. 12, pp. 2419-2426, December 1989.

66.          I. Sen Gupta and A. Rakshit, “A parallel algorithm for the determination of all cliques of a symmetric graph'”, Journal of IETE, India, Vol. 33, No. 1, Jan-Feb 1987.

67.          I. Sen Gupta, “On the syndrome testing of syndrome-untestable combinational circuits by the addition of extra observation points”, Journal of IETE, India, Vol. 33, No. 3, May-June 1987.

68.          I. Sen Gupta and P. Mukherjee, “On reachability and reaching matrices of a directed graph”, FEEDBACK Journal, Vol. 10, No.7-9, 1987.

69.          I. Sen Gupta and P. Mukherjee, “Determination of vertex cutsets of a graph”, Bulletin of the Calcutta Mathematical Society, Vol. 80, No. 2, pp. 127-132, April 1988.

70.          I. Sen Gupta, P. Mukherjee and T. Mukherjee, “An algorithmic approach for determining the complete k-partiteness of a graph”, Bulletin of the Calcutta Mathematical Society, Vol. 80, No. 2, pp. 137-142, April 1988.

 

Publications in Proceedings of Seminars/Conferences

1.             V. Agarwal, A. SIngla, M. Samiuddin, S. Roy, T-Y. Ho, I. Sengupta and B.B. Bhattacharya, “Reservoir and mixer constrained scheduling for sample preparation on digital microfluidic biochips”, 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 702-707, 2017.

2.             P.M.N. Rani, A. Kole, K. Datta, I. Sengupta, “Improved Decomposition of Multiple-Control Ternary Toffoli Gates Using Muthukrishnan-Stroud Quantum Gates”, 9th International Conference on Reversible Computation, pp. 202-213, Kolkata, India, 2017.

3.             L. Marbaniang, A. Kole, K. Datta, I. Sengupta, “Design of Efficient Quantum Circuits Using Nearest Neighbor Constraint in 2D Architecture”, 9th International Conference on Reversible Computation, pp. 248-253, Kolkata, India, 2017.

4.             A. Kole, R. Wille, K. Datta, I. Sengupta , “Test pattern generation effort evaluation of reversible circuits ”, 9th International Conference on Reversible Computation, pp. 162-175, Kolkata, India, 2017.

5.             A. Kole, P.M.N. Rani, K. Datta, I. Sengupta, R. Drechsler, “Exact Synthesis of Ternary Reversible Functions Using Ternary Toffoli Gates”, IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL), pp. 179-184, Novi Sad, Serbia, 2017.

6.             K. Datta and I. Sengupta, “Memristors: Technology, Circuit Models and Applications (Half-Day Tutorial)”, 30th International Conference on VLSI Design (VLSID), Hyderabad, India, 2017.

7.             A. Kole, K. Datta, “Improved NCV Gate Realization of Arbitrary Size Toffoli Gates”, 30th International Conference on VLSI Design (VLSID), pp 289-294, Hyderabad, India, 2017.

8.             R. Karmakar, N. Prasad, S. Chattopadhyay, R. Kapur and I. Sengupta, “A new logic encryption strategy ensuring key interdependency”, 30th International Conference on VLSI Design (VLSID), Hyderabad, India, 2017.

9.             A. Kole, K. Datta, R. Wille and I. Sengupta, “A nearest neighbour quantum cost metric for the reversible circuit level”, IEEE Region 10 Conference (TENCON), pp. 2943-2948, Penang, Malayasia, 2017.

10.         P.L. Thangkhiew, R. Gharpinde, D.N. Yadav, K. Datta and I. Sengupta, “Efficient implementation of adder circuits in memristive crossbar array”, IEEE Region 10 Conference (TENCON), pp. 207-212, Penang, Malayasia, 2017.

11.         P.L. Thangkhiew, R. Gharpinde, P.V. Chowdhary; K. Datta, I. Sengupta, “Area Efficient Implementation of Ripple Carry Adder using Memristor Crossbar Arrays”, 11th International Design & Test Symposium (IDT), pp 142-147, Hammamet, Tunisia, 2016.

12.         S. Burman, K. Datta, R. Wille, I. Sengupta, R. Drechler, “An Improved Gate Library for Logic Synthesis of Optical Circuits”, 6th International Symposium on Embedded Computing and System Design (ISED), pp. 1-6, Patna, India, 2016.

13.         R. Shrivastwa, K. Datta, I. Sengupta, “Fast Qubit Placement in 2D Architecture Using Nearest Neighbor Realization”, IEEE International Symposium on Nanoelectronic and Information Systems, pp. 95-100, India, 2015.

14.         P.M. Arpita, K. Datta, R. Vemula, I. Sengupta, “Optimization of Reversible Circuits using Triple-Gate Templates at Quantum Gate Level”, International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV), pp. 120-124, Shillong, India, 2015.

15.         K. Datta, A. Gokhale, I. Sengupta, H. Rahaman, “An ESOP-based Reversible Circuit Synthesis Flow using Simulated Annealing”, Applied Computation and Security Systems, pp. 131-144, Kolkata, India, 2015.

16.         K. Manna, V. S. Teja, S. Chattopadhyay and I. Sengupta, “TSV placement and core mapping for 3D mesh based network-on-chip design using extended Kernighan-Lin algorithm”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2015 (Accepted).

17.         A. Kole, K. Datta, I. Sengupta and R. Wille, “Towards a cost metric for nearest neighbor constraints in reversible circuits”, Proc. 7th Intl. Conf. on Reversible Computation (RC-2015), pp. 273-278, Grenoble, France, July 2015.

18.         E. Schonborn, K. Datta, R. Wille, I. Sen Gupta, H. Rahaman and R. Drechsler, “BDD-based synthesis for all-optical Mach-Zehnder interferometer circuits”, Proc. 28th Intl. Conf. on VLSI Design (VLSI-2015), pp. 435-440, Bangalore, India, January 2015.

19.         S. Chakraborti, P. V. Chowdhary, K. Datta and I. Sengupta, “BDD based synthesis of Boolean functions using memristors”, Prof. 9th Intl. Design and Test Symposium (IDT-2014), pp. 136-141, Algiers, Algeria, December 2014.

20.         K. Manna, S. Chattopadhyay and I. Sengupta, “Through silicon via placement and mapping strategy for 3D mesh based network-on-chip”, 22nd Intl. Conference on Very Large Scale Integration (VLSI-SoC), pp. 1-6, 2014.

21.         E. Schonborn, K. Datta, R. Wille, I. Sen Gupta, H. Rahaman and R. Drechsler, “Optimizing DD-based synthesis of reversible circuits using negative control lines”, 17th Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS-2014), Warsaw, Poland, April 2014.

22.         K. Datta, A. Gokhale, I. Sengupta and H. Rahaman, “An ESOP based reversible circuit synthesis flow using simulated annealing”, Intl. Doctoral Symposium on Applied Computation and Security Systems (ACSS), Kolkata, India, April 2014.

23.         K. Datta and I. Sen Gupta, “All optical reversible multiplexer design using Mach-Zehnder Interferometer”, Proc. 27th Intl. Conf. on VLSI Design (VLSI-2014), pp. 539-544, Mumbai, India, January 2014.

24.         A. Chatterjee, M. Kaushal and I. Sen Gupta, “Accelerating sorting of encrypted data”, Proc. 14th Intl. Conf. on Cryptology in India (INDOCRYPT-2013), Mumbai, India, December 2013.

25.         B. Ghoshal and I. Sen Gupta, “A distributed BIST scheme for NoC-based memory cores”, Proc. 16th Euromicro Conf. on Digital System Design (DSD-2013), Santander, Spain, September 2013.

26.         S. Kundu, S. Chattopadhyay, I. Sen Gupta and R. Kapur, “An ATE assisted DFD technique for volume diagnosis in scan chains”, Proc. 50th ACM/IEEE Design Automation Conference (DAC-2013), Austin, USA, June 2013.

27.         K. Datta, B. Ghuku, D. Sandeep, I. Sen Gupta and H. Rahaman, “A cycle-based reversible logic synthesis approach”, Proc. 3rd Intl. Conf. on Advances in Computing and Communications (ACC-2013), Kochi, India, August 2013.

28.         K. Datta, G. Rathi, R. Wille, I. Sen Gupta, H. Rahaman and R. Drechsler, “Exploiting negative control lines in the optimization of reversible circuits”, Proc. 5th Intl. Conf. on Reversible Computation (RC-2013), Victoria, Canada, July 2013.

29.         K. Datta, G. Rathi, I. Sen Gupta and H. Rahaman, “An improved reversible circuit synthesis approach using clustering of ESOP cubes”, 17th Reed-Muller Workshop (RM-2013), Toyoma, Japan, May 2013.

30.         K. Datta, V. Srivastav, I. Sen Gupta and H. Rahaman, “Reversible logic implementation of AES algorithm”, Proc. 8th Intl. Conf. on Design and Technology of Integrated Systems (DTIS-2013), Abu Dhabi, UAE, March 2013.

31.         S. Kundu, S. Chattopadhyay, I. Sen Gupta and R. Kapur, “Aggressive scan chain masking for improved diagnosis of multiple scan chain failures”, Proc. 18th IEEE European Test Symposium (ETS-2013), Avignon, France, May 2013.

32.         A.K. Singh, S. Dhal and I. Sen Gupta, “An approach to solve tracking and message blocking problems in RFID”, Proc. 4th Intl. Conf. on Communications Security and Information Assurance (CSIA-2013), New Delhi, India, May 2013.

33.         A. Basu, I. Sen Gupta and J.K. Sing, “Formal security verification of secured ECC based signcryption scheme”, Proc. 3rd Intl. Conf. on Communications Security and Information Assurance (CSIA-2012), Springer-Verlag, Vol. 167, pp. 713-725, 2012.

34.         A. Basu and I. Sen Gupta, “Improved secure dynamic key management scheme with access control in user hierarchy”, Proc. DICTAP-2012, pp. 220-225, Bangkok, Thailand, May 2012.

35.         K. Datta, I. Sen Gupta and H. Rahaman, “Group theory based reversible logic synthesis”, Proc. 5th Intl. Conf. on Computers and Devices for Communication (CODEC-2012), Kolkata, India, December 2012.

36.         K. Datta, I. Sen Gupta and H. Rahaman, “Reversible circuit synthesis using evolutionary algorithm”, Proc. 5th Intl. Conf. on Computers and Devices for Communication (CODEC-2012), Kolkata, India, December 2012.

37.         K. Datta, I. Sen Gupta, H. Rahaman and R. Drechsler, “An evolutionary approach to reversible logic synthesis using output permutation”, Prof. 7th Intl. Design and Test Symposium (IDT-2012), Doha, Qatar, December 2012.

38.         K. Datta and I. Sen Gupta, “Particle swarm optimization based circuit synthesis of reversible logic”, Prof. 3rd Intl. Symp. On Electronic System Design (ISED-2012), Kolkata, India, December 2012.

39.         S. Dhal and I. Sen Gupta, “A new authentication protocol for multi-tag RFID”, Proc. RAIT-2012, July 2012.

40.         S. Dhal and I. Sen Gupta, “A new authentication protocol for multi-tag RFID applicable to passive tag”, Proc. 2nd Intl. Conf. on Communication, Computing and Security, 2012.

41.         K. Datta, G. Rathi, I. Sen Gupta and H. Rahaman, “Synthesis of reversible circuits using heuristic search method”, Proc. 25th Intl. Conference on VLSI Design (VLSI-2012), Hyderabad, India, January 2012.

42.         S. Kundu, S. Chattopadhyay, I. Sen Gupta and R. Kapur, “Multiple fault diagnosis based on multiple fault simulation using particle swarm optimization”, Proc. Intl. Conference on VLSI Design (VLSI-2012), Hyderabad, India, January 2012.

43.         A. Chatterjee and I. Sen Gupta, “FPGA implementation of binary Edwards curve using ternary representation”, Proc. GLSVLSI-2011, EPFL Campus, Lausanne, Switzerland, May 2011.

44.         K. Datta and I. Sen Gupta, “Improving bitrate in detail coefficient based audio watermarking using wavelet transformation”, Proc. International Conference on Communications and Signal Processing (ICCSP-2011), February 10-12, 2011, Kerala, India.

45.         M.K. Dasmohapatra, K. Datta and I. Sen Gupta, “A preventive measure to protect from denial of service attack”, Proc. Fourth International Conference on Network Security and Applications (CNSA-2011), July 15-17, 2011, Chennai, India.

46.         A. Basu, J.K. Singh and I. Sen Gupta, “Verifiable (t,n) threshold secret sharing scheme using ECC based signcryption:, Proc. International Conference on Information Systems, Technology and Management, Bangkok, Springer (2010). 

47.         K. Datta and l. Sen Gupta, “A robust encrypted audio watermarking scheme using discrete wavelet transformation”, Proc. 13th World Multi-Conference on Systemics, Cybernetics and Informatics (WMSCI 2009), Orlando, USA,  (2009). 

48.          I. Datta, K. Datta and I. Sen Gupta, “EXE watermarking by exploring the binary format for executables in Windows and Unix”, Proc. Indo-US Conference & Workshop on Cyber Security, Cyber Crime and Cyber Forensics, December 2009, Kochi, India. 

49.         K. Datta and I. Sen Gupta, “A redundant audio watermarking technique using discrete wavelet transformation”, Proc. 2nd International Conference on Communication Software and Networks (ICCSN 2010), Singapore, IEEE Computer Society Press (2010). 

50.         M. Saha, I. Sen Gupta and D. Roy Chowdhury, “A DDH-based group key agreement protocol for mobile environment”, Proc. IEEE COMSNET 2009, January 5-10, 2009, Bangalore, India.

51.         V. Bhat, I. Sen Gupta and A. Das, “Audio watermarking based on BCH coding using CT and DWT”, Proc. ICIT’08, IEEE Computer Society Press, December 17-20, 2008, Bhubaneswar, India.

52.         V. Bhat, I. Sen Gupta and A. Das, “Audio watermarking based on mean quantization in cepstrum domain”, Proc. ADCOM’08, IEEE Computer Society Press, pp. 73-77, December 14-17, 2008, Chennai, India.

53.         T. De, P. Jain, A. Pal and I. Sen Gupta, “A genetic algorithm based approach for traffic grooming, routing and wavelength assignment in optical WDM mesh networks”, Proc. 16th IEEE Intl. Conf. on Networks (ICON’08), December 12-14, 2008, New Delhi, India.

54.         T. De, P. Jain, A. Pal and I. Sen Gupta, “A multi-objective evolutionary algorithm based approach for traffic grooming, routing and wavelength assignment in optical WDM networks”, Proc. IEEE Region 10 Colloquium, December 8-10, 2008, Kharagpur, India.

55.         V. Bhat, I. Sen Gupta and A. Das, “Audio watermarking based on quantization in wavelet domain”, Proc, ICISS’08, LNCS-5352, pp. 235-242, 2008.

56.         M. Saha, D. Roy Chowdhury and I. Sen Gupta, “A key agreement protocol for group communication”, Proc. National Workshop on Cryptology, September 8-10, 2008, Hyderabad, India.

57.         M. Saha, D. Roy Chowdhury and I. Sen Gupta, “A secure verifiable key agreement protocol for mobile conferencing”, Proc. COMSWARE 2008, pp. 219-222, January 5-10, 2008, Bangalore, India.

58.         T. De, A. Pal and I. Sen Gupta, “Routing and wavelength assignment in all optical networks based on clique partitioning”, Proc. ICDCN’08, LNCS-4904, pp. 452-463, January 5-8, 2008, Kolkata, India.

59.         M. Alam, S. Ghosh, D. Roy Chowdhury and I. Sen Gupta, “Single chip encryptor/decryptor core implementation of AES algorithm”, Proc. 21st Intl Conference on VLSI Design, January 2008, New Delhi, India.

60.         A.K. Das and I. Sen Gupta, “A key establishment scheme for large-scale mobile wireless sensor networks”, Proc. ICDCIT’07, LNCS-4882, pp. 79-88, 2007.

61.         A. Jain and I. Sen Gupta, “A JPEG compression resistant steganography scheme for raster graphics image”, Proc. IEEE TENCON 2007, October 30 – November 2, 2007, Taipei, Taiwan.

62.         M. Bubna, N. Goyal and I. Sen Gupta, “A DFT methodology for detecting bridging faults in reversible logic circuits”, Proc. IEEE TENCON 2007, October 30 – November 2, 2007, Taipei, Taiwan.

63.         S. Ghosh, M. Alam, D. Roy Chowdhury and I. Sen Gupta, “Effect of side channel attacks on RSA embedded devices”, Proc. IEEE TENCON 2007, October 30 – November 2, 2007, Taipei, Taiwan.

64.         M. Saha, M. Kedia and I. Sen Gupta, “A robust digital watermarking scheme for media files”, Proc. IEEE TENCON 2007, October 30 – November 2, 2007, Taipei, Taiwan.

65.         S. Ghosh, M. Alam, I. Sen Gupta and D. Roy Chowdhury, “A robust GF(p) parallel arithmetic unit for public key cryptography”, Proc. 33rd EUROMICRO Conference SEAA 2007, pp. 109-117, August 28-31, 2007, Lubeck, Germany.

66.         M. Alam, S. Ghosh, D. Mukhopadhyay, D. Roy Chowdhury and I. Sen Gupta, “Latency optimized AES-Rijndael with flexible mode of operation”, Proc. VDAT 2007, pp. 413-420, August 8-11, 2007, Kolkata, India.

67.         S. Ghosh, D. Roy Chowdhury and I. Sen Gupta, “Side channel attacks on RSA and ECC crypto devices”, Proc. National Workshop on Cryptology, 2007, Coimbatore, India.

68.         M. Alam, D. Roy Chowdhury, S. Ghosh and I. Sen Gupta, “Side channel attack setup: different issues for DPA and SPA”, Proc. National Workshop on Cryptology, 2007, Coimbatore, India.

69.         M. Alam, S. Roy, D. Mukhopadhyay, S. Ghosh, D. Roy Chowdhury and I. Sen Gupta, “An area optimized reconfigurable encryptor for AES-Rijndael”, Proc. Design, Automation and Test in Europe (DATE 2007), pp. 1116-1121, April 17-19, 2007, Nice, France.

70.         M. Alam, S. Ghosh, D. Mukhopadhyay, D. Roy Chowdhury and I. Sen Gupta, “An efficient reconfigurable encryptor for AES-Rijndael with S-box optimization”, Proc. 15th ACM/SIGDA Intl Symposium on Field Programmable Gate Arrays (FPGA 2007), February 18-20, 2007, California, USA.

71.         M. Saha, D. Roy Chowdhury and I. Sen Gupta, “An improved end-to-end secure authentication scheme for CDMA networks”, Proc. 4th IASTED Asian Conference on Communication Systems and Networks, April 2-4, 2007, Phuket, Thailand.

72.         A. Basu and I. Sen Gupta, “Performance analysis of distance vector routing protocol through simulation”, Proc. International Conference on IT, March 19-21, 2007, Haldia, India.

73.         A. Duttagupta, A. Bishnu, and I. Sen Gupta, “Optimization problems on the maximal breach path measure for wireless sensor network coverage”, Proc. ICDCIT 2006, December 20-23, 2006, Bhubaneswar, India.

74.         B.B. Paul, R. Mukhopadhyay, and I. Sen Gupta, “Genetic algorithm based scan chain optimization using physical information”, Proc. IEEE Tencon 2006, November 17-20, 2006, Hong Kong.

75.         S. Roy, M. Alam, D. Mukhopadhyay, D. Roy Chowdhury and I. Sen Gupta, “Design of a predictor for MOS based cryptographic systems: a TVAC-PSO based approach”, Proc. IASTED Intl Conference on Modelling, Simulation and Optimization (MSO 2006), September 11-13, 2006, Gaborone, Botswana.

76.         M. Saha, D. Roy Chowdhury and I. Sen Gupta, “CDMA-I: an improved authentication scheme for CDMA networks”, Proc. National Workshop on Cryptology, September 8-10, 2006, Pune, India.

77.         M. Saha and I. Sen Gupta, “A new approach to encrypted steganography”, Proc. Intl. Conf. on Computer and Communication Engg. (ICCCE’06), pp. 87-93, May 9-11, 2006, Kuala Lumpur, Malaysia.

78.         B.B. Paul, R. Mukhopadhyay, S. Banerjee, and I. Sen Gupta, “Routing-aware multi-scan chain optimization technique for low power testing”, Proc. Intl. Conf. on Computer and Communication Engg. (ICCCE’06), pp. 1248-1253, May 9-11, 2006, Kuala Lumpur, Malaysia.

79.         P. Ghosh, B.B. Paul and I. Sen Gupta, “An approach to reduce power by scan chain partitioning and flip-flop reordering”, Proc. RTET-06, February 25, 2006, Kolkata, India.

80.         M. Saha and I. Sen Gupta, “A new steganography implementation using randomization of addresses”, Proc. RTET-06, February 25, 2006, Kolkata, India.

81.         M. Saha and I. Sen Gupta, “Survivability analysis in a static virtual topology design in optical networks”, Proc. EAIT-06 (Elsevier), pp. 247-250, February 11-12, 2006, Kolkata, India. 

82.         M. Saha and I. Sen Gupta, “A unified approach to designing reliable network topology”, Proc. 5th Intl. Conference on Networking (ICN’06), April 23-26, 2006, Mauritius. 

83.         V. Arora and I. Sen Gupta, “A unified approach to partial scan design using genetic algorithm”, Proc. 14th Asian Test Symposium (ATS 2005), December 18-21, 2005, Kolkata, India.

84.         M. Saha and I. Sen Gupta, “A genetic algorithm based approach for static virtual topology design in optical networks”, Proc. IEEE Indicon, December 11-13, 2005, Chennai, India. 

85.         M. Saha and I. Sen Gupta, “A multistage interconnection network with real-time fault detection and avoidance capabilities”, Proc. 8th Intl. Conference on Information Technology (CIT-2005), December 2005, Bhubaneswar, India. 

86.         N. Jha and I. Sen Gupta, “A new scheme to improve the security of the WEP protocol”, Proc. of the Intl. Conference on Communication, Network and Information Security (CNIS-2003), pp.1-6, December 10-12, 2003, New York, USA. 

87.         N. Choudhury and I. Sen Gupta, “Design and implementation of an IP core for the TCP/IP protocol stack”, Proc. of the 6th Intl. Conference on Information Technology (CIT-2003), December 2003, pp. 324-329, Bhubaneswar, India. 

88.         P. Ratanchandani, H.K. Pati, R. Mall and I. Sen Gupta, “A framework to provide QoS guarantees in mobile cellular networks”, Proc. of the 6th Intl. Conference on Information Technology (CIT-2003), pp. 211-215, December 2003, Bhubaneswar, India.

89.         R. Dutta, S. Ghose and I. Sen Gupta, “Lightpath provisioning in wavelength selective WDM networks using GMPLS”, Proc. of the 6th Intl. Conference on Information Technology (CIT-2003), pp. 36-41, December 2003, Bhubaneswar, India.

90.         N. Jha and I. Sen Gupta, “A generalized scheme for multiparty secure access using elliptic curve cryptography”, Proc. of the 6th Intl. Conference on Information Technology (CIT-2003), pp. 119-124, December 2003, Bhubaneswar, India.

91.         S.S. Mahadevan, I. Sen Gupta and P.K.J. Mohapatra, “Website authentication - integrating zero knowledge proof and probabilistic algorithm”, Proc. of the 6th Intl. Conference on Information Technology (CIT-2003), pp. 125-130, December 2003, Bhubaneswar, India. 

92.         R. Datta, S. Ghose and I. Sen Gupta, “A rerouting technique with minimum traffic disruption for dynamic traffic in WDM networks”, Proc. of the 11th IEEE Conf. on Networks (ICON), pp. 425-430, Sept. 28 – Oct. 1, 2003, Sydney, Australia.

93.         N. Jha and I. Sen Gupta, “New schemes for authentication and encryption using elliptic curve cryptography”, Proc. of the Intl. Conf. on Information Technology (ITPC-2003), pp. 343-348, May 2003, Kathmandu, Nepal. 

94.         S.S. Mahadevan, I. Sen Gupta, and P.K.J. Mohapatra, “Refined non-interactive zero knowledge authentication scheme for commercial web sites”, Proc. of the Intl. Conf. on Information Technology (ITPC-2003), pp. 137-144, May 2003, Kathmandu, Nepal. 

95.         R. Datta, S. Ghose and I. Sen Gupta, “New scheme for design of static virtual topology in wide area optical networks”,  Proc. 4th International Workshop on Distributed Computing,  LNCS-2571, pp-280-289, December 2002, Kolkata, India.

96.         S. Basu, D. Mukhopadhyay, D. RoyChowdhury, I. Sen Gupta, and S. Bhawmik, “Reformatting test patterns for testing embedded core based system using test access mechanism (TAM) switch”, Proc. of the Intl. Conference on VLSI Design 2002, pp. 598-603, Bangalore, India.

97.         P. Kulkarni and I. Sen Gupta, “Multiple token based approaches for load balancing”,  Proc. International Conference on Parallel and Distributed Computing Systems (PDCS'2000), August 1999, Las Vegas, USA.

98.         P. Kulkarni and I. Sen Gupta, “A new approach for load balancing using differential load measurement (DLM)”, Proc. IEEE International Conference on Information Technology, ITCC'2000, March 2000, Las Vegas, USA.

99.         P. Kulkarni and I. Sen Gupta, “Load balancing using multiple token policy”, Proc. IEEE International Conference on Parallel and Distributed Systems and Applications PDSA'2000, June 2000, TakiLab Japan.

100.     P. Kulkarni and I. Sen Gupta, “Dual token based load balancing on network of workstations (DTLB)”, Proc. International Conference on Applied Informatics, AI'2000, February 2000, Insbruch, Austria.

101.     P. Kulkarni and I. Sen Gupta, “Load balancing using load graphs”, Proc. National Conference on Communication NCC'99, January 1999, Kharagpur, India.

102.     P. Kulkarni and I. Sen Gupta, “Load graph based transfer method (LoGTra) for dynamic load balancing on network of workstations”, Proc. International Conference on Parallel and Distributed Systems PDCS'98 Las Vegas, USA.

103.     P. Kulkarni and I. Sen Gupta, “Fault tolerant system for distributed learning environment and dynamic load distribution on network of workstations”, Proc. International Conference on Distributed Learning, February 1998, IGNOU, New Delhi.

104.     G.P. Biswas and I. Sen Gupta, “A design technique of TSC checker for Borden's code”, Proc. VLSI Design '97, pp. 529-530, January 1997.

105.     G.P. Biswas and I. Sen Gupta, “Design of t-UED/AUED codes from Berger's AUED cod”, Proc. VLSI Design '97, pp. 364-369, January 1997.

106.     G.P. Biswas and I. Sen Gupta, “Generalized modular design of testable m-out-of-n code checker”, in  Proc. 4th Asian Test Symposium, pp. 322-326, November 23-24, 1995, Bangalore, India.

107.     U.K. Bhattacharya, I. Sen Gupta, S. Shyama Nath and P. Dutta, “On the synthesis and testing if hazard-free logic'', Proc. VLSI Design '95, pp. 121-124, January 1995, New Delhi, India.

108.     G.P. Biswas and I. Sen Gupta, “Design of t error correcting and all unidirectional error detecting codes using cellular automata”, Proc. First Conference on Fault-Tolerant Systems and Software, pp. 134-140, IIT Madras, December 20-22, 1995.

109.     G. Bandyopadhyay, I. Sen Gupta and T.N. Saha, “Design and implementation of a diakoptic based distributed Newton-Raphson load flow algorithm”, Proc. 8th National Power Systems Conference, pp.358-362, December 14-17, 1994, New Delhi, India.

110.     U.K. Bhattacharya and I. Sen Gupta, “A new approach for test generation of CMOS combination circuits”, Proc. Intl. Conf. on Computer Systems and Education, pp. 283-284, June 22-25, 1994. Bangalore, India.

111.     C. Biswas and I. Sen Gupta, “Technology mapping for lookup table based FPGAs using genetic algorithm”, Proc. Intl. Conf. on Computer Systems and Education, pp. 224-235, June 22-25, 1994, Bangalore, India.

112.     R. Agarwal and I. Sen Gupta, “On the synthesis of gate matrix layout, Proc.  VLSI Design '94, pp. 203-206, January 1994, Calcutta, India.

113.     R. Agarwal, I. Sen Gupta and U.K. Bhattacharyya, “On the reduction of area in gate matrix layout”, Proc. Indian Computing Congress, pp. 72-79, December 1992, Hyderabad, India.

114.     U.K. Bhattacharyya, S. Senthil, I. Sen Gupta and P.P. Das, “A parallel implementation of fault simulation algorithm”, Proc. Indian Computing Congress, India, pp. 63-71, December 1992.

115.     D. Roy Chowdhury, S. Basu, I. Sen Gupta and P. Pal Chaudhuri, “Encoding and decoding of error correcting codes using cellular automata”, Proc. VLSI Design '92, pp. 133-136, January 1992, Bangalore, India.

116.     D. Roy Chowdhury, I. Sen Gupta and P. Pal Chaudhuri, “A fast retrieval memory system design using Cellular Automata”, Proc. VLSI Design '92, pp. 157-160, January 1992, Bangalore, India.

117.     D. Roy Chowdhury, I. Sen Gupta and P. Pal Chaudhuri, “A programmable cellular automata structure for built-in self-test”, Proc. IEEE Tencon  '91, pp. 166-170, August 28-30, New Delhi, India.

118.     D. Roy Chowdhury, S. Basu, I. Sen Gupta and P. Pal Chaudhuri, “A novel scheme of designing error correcting codes using cellular automata”, Proc. IEEE Tencon '91, pp. 231-235, New Delhi, India.

119.     I. Sen Gupta and D. Roy Chowdhury, “A fast fault simulator for sequential logic circuits”, Proc. IEEE Tencon '91, pp. 180-184, August 28-30, New Delhi, India.

120.     I. Sen Gupta, “Index vector testing : a comparative study”, Proc. A.K. Chaudhuri Commemoration Symposium on Circuits, Systems and Computers, Calcutta University, February 1990.

121.     I. Sen Gupta, “A structured approach to designing digital sequential circuits for testability”, Proc. Intl. Conf. on Fault-Tolerant Systems and Diagnostics, September 1989, Czechoslovakia.

122.     I. Sen Gupta and D. Roy Chowdhury, “A structured approach to designing digital sequential circuits for testability”, Proc. NACONECS-89, pp. 34-36, November 1989, Roorkee, India.

123.     I. Sen Gupta and D. Roy Chowdhury, “A new fault model and its applicability to syndrome and index vector testing”, Proc. Seminar on Parallel Processing Systems and  their Applications  (PPSTA),  pp.  224-228, Institution of Engineers, December 1988, Calcutta, India.

124.     I. Sen Gupta and D. Roy Chowdhury, “Design of a combinational circuit tester based on index vector testing”, Proc. Intl. Symp. on Electronic Devices, Circuits and Systems, pp. 627-629, December 1987, Kharagpur, India.

125.     I. Sen Gupta, “Index vector testing of combinational circuits”, Proc. International Test Conference 1987, pp. 1108-1112, September 1987, Washington D.C., U.S.A.

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