Research/Consultancy Projects Completed/Ongoing:
|
Sl. No. |
Title |
Sponsor |
Role |
Duration |
Fund |
Status |
|
1. |
Mapping quantum circuits to dedicated architectures subject to
technological constraints |
DST,
Government of India (Indo-Austria) |
PI |
2
years |
9.7 lakhs |
Accepted |
|
2. |
Efficient realization of quantum gate operations incorporating
parallelism and fault tolerance |
DST,
Government of India |
PI |
3
years |
47.8 lakhs |
Accepted |
|
3. |
Efficient and adaptive mapping and testing of quantum circuits in IBM
QX and nearest neighbor architectures |
DST,
Government of India |
Co-PI |
3
years |
43.5 lakhs |
Accepted |
|
4. |
Developing design-for-security techniques in integrated circuits via
logic encryption |
DeitY, Government of India |
Co-PI |
3
years (2018-2021) |
15.9 lakhs |
Ongoing |
|
5. |
Security concerns in a scan compression environment for DFTMAX Ultra |
Synopsys
India |
Co-PI |
3
years (2017-2020) |
49.8 lakhs |
Ongoing |
|
6. |
Thermal aware testing of VLSI circuits and systems |
DeitY, Government of India |
Co-PI |
3
years (2011-2014) |
49.9 lakhs |
Completed |
|
7. |
Design of side channel attack resistant programmable block ciphers on
FPGA |
DeitY, Government of India |
Co-PI |
3
years (2010-2013) |
73.2 lakhs |
Completed |
|
8. |
Design and development of an integrated security risk management
system of an enterprise network |
DeitY, Government of India |
Co-PI |
3
years (2010-2013) |
63.1 lakhs |
Completed |
|
9. |
Strategies for thermal aware network on chip design |
DeitY, Government of India |
Co-PI |
3
years (2013-2016) |
25.0 lakhs |
Completed |
|
10. |
Power aware mesh-of-tree NOC design |
DeitY, Government of India |
Co-PI |
3
years (2009-2012) |
17.9 lakhs |
Completed |
|
11. |
Fundamental research in information assurance |
HQ-IDS,
Ministry of Defence |
PI |
4
years (2006-2010) |
48.0 lakhs |
Completed |
|
12. |
Development
of centre of excellence in information assurance |
HQ-IDS,
Ministry of Defence |
PI |
2 years (2006-2008) |
50.0 lakhs |
Completed |
|
13. |
Strategies for reducing power consumption during VLSI circuit testing |
Synopsys India |
PI |
3 years (2007-2010) |
54.0 lakhs |
Completed |
|
14. |
Strategies for power reduction during VLSI testing |
Department of Information Technology, Government of India |
Co-PI |
2 years |
31.0 lakhs |
Completed |
|
15. |
Linux kernel software development and support |
Nucleodyne
Systems Inc., USA |
PI |
3 years (2004-2007) |
15.0 lakhs |
Completed |
|
16. |
Feasibility studies on upliftment
of science and technology in Dubai |
Educare Ltd. |
PI |
6 months |
2.0 lakhs |
Completed |
|
17. |
Design and implementation
of a cryptosystem resistant to vulnerabilities and side channel attacks |
Department of Information Technology, Government of India |
PI |
3 years (2005-2008) |
138.0 lakhs |
Completed |
|
18. |
Design of a 16-bit
microcontroller with error detection and correction (EDAC) facility |
Indian Space Research Organization, Bangalore |
PI |
2 years (2003-2005) |
14.0 lakhs |
Completed |
|
19. |
Design of an IP core for a
digital signal processor (DSP) with essential functionalities |
Indian Space Research Organization, Bangalore |
PI |
2 years (2003-2005) |
10.5 lakhs |
Completed |
|
20. |
Curriculum development in
the area of VLSI testing |
Intel Technology Pvt. Ltd., India |
PI |
18 months |
3.0 lakhs |
Completed |
|
21. |
Testing of core based
systems |
Agere
Systems, USA |
PI |
1 year |
12.0 lakhs |
Completed |